1. Technical Field
The invention relates generally to MOS transistors. More specifically, the invention relates to the improvement of drive-strength and leakage of deep submicron MOS transistors.
2. Description of the Prior Art
Conventional complementary metal-oxide semiconductor (CMOS) technology currently poses some difficult problems as the minimum feature size shrinks to below 100 nanometers and power supply voltage is reduced to less than 1.0V. A typical layout of a 0.18 micron transistor 100 is shown in FIG. 1. The transistor is manufactured over a well 110 where a diffusion area 120 is created. The gate 130 of the transistor 100 is formed over the well 120 and has a width “w,” for example 0.18 micron, as a minimum width for a transistor in a 0.18 micron technology. Contacts 140 and 141 comprise one terminal of the NMOS transistor, for example the drain, and a contact 150 provides another terminal of the transistor 100, for example the source. The contact 131 is connected to the gate 130. There are other minimal feature sizes, such as a minimal size for the well “x” and a minimum distance from the edge of the well to the diffusion area 120 marked as “y.” Dimensions such as “w,” “x,” and “y” are generally process dependent. The power supply voltage is reduced in correspondence with the minimum feature size to maintain a limit on the electrical field across the oxide. Therefore, the power supply voltage has decreased from 3.3V for 0.35-micron CMOS technology to 1.8V for 0.18 micron technology, and is further expected to be at the 1.0V level for 100 nanometers CMOS technology. While power supply voltage decreased, the threshold voltage of the NMOS transistors stayed between 0.45V and 0.35V. The relationship between the NMOS threshold voltage Vth and CMOS power supply VDD is known to be very critical. The threshold voltage determines the leakage current, Ioff, of the transistor when it is in its OFF state. As the threshold voltage is driven lower, the leakage current increases.
The drain current of a transistor is a direct function of the overdrive of the transistor, measured as the difference between power supply VDD and threshold voltage Vth. The drain current of the transistor determines the time required to charge the load capacitance from ground to the level of power supply VDD. This overdrive voltage has decreased constantly as the power supply decreased from 3.3V to 1.0V, while threshold voltage decreased only from 0.45V to 0.35V. For 0.1 micron technology, the threshold voltage of the transistors is being scaled below 0.35V at the expense of a very high OFF stage leakage current IOFF which ranges between 10 nA to 100 nA for a transistor with equal gate length and width, or a W/L ratio of 1. For a transistor with a gate width to length (W/L) ratio of 10, the OFF current increases to ten times the value stated above, i.e. from 100 nA to 1000 nA. For a CMOS technology of 0.1-micron minimum feature size, a typical VLSI chip is expected to contain over 100 million gates. Thus, a leakage of every gate of 1 microamperes results in 100 amperes of leakage current.
A scheme to control the threshold voltage dynamically has been proposed by Takamiya et al. in an article titled High Performance Electrically Induced Body Dynamic Threshold SOI MOSFET (EIB-DTMOS) with Large Body Effect and Low Threshold Voltage. Takamiya et al. suggest a scheme that shorts the gate and the substrate of the transistors, thereby causing the substrate voltage of the transistor to increase as the gate voltage is increased for a n-channel MOS (NMOS) transistor. This scheme is proposed for NMOS transistors fabricated on silicon-on-insulator (SOI) substrates where the transistor substrate is totally isolated. This scheme manipulates the threshold voltage by changing the bias of the substrate in the positive direction for a NMOS transistor along with a positive signal at the gate. As the substrate to source voltage becomes positive, the depletion layer width is reduced. This results in a lower threshold voltage of the transistor, thereby increasing the current from the transistor. In the native form, the Takamiya et al. invention is applicable only for circuits using power supply voltage of less than 0.6V because this scheme turns on the substrate-to-source diode. The leakage from this diode must be limited. Otherwise, one type of leakage would be traded for another, i.e. from drain-to-source leakage to substrate-to-source leakage.
Douseki in U.S. Pat. No. 5,821,769 describes a method for the control of the threshold voltage of a MOS transistor by connecting a MOS transistor between the gate and the substrate to control the threshold voltage. The Douseki invention requires the addition of another transistor for every transistor whose threshold voltage is dynamically controlled. The adjusted threshold voltage is fixed by the power supply voltage and the threshold voltage of the additional transistor. The area penalty is fairly large for the Douseki invention, although it can be executed without additional process steps.
There is a therefore a need in the art for a technology which can reduce the leakage of MOS transistors without adversely affecting the drive current or the drain current under saturation conditions, which conditions are stated as drain-source voltage and gate-source voltage equal to the power supply voltage (VDS=VGS=VDD).